The present invention is directed to improved techniques for forming silicon-on-insulator (SOI) films for use in integrated circuits, particularly in providing an improved encapsulation layer for zone-melt recrystallization of SOI films.
The technology for manufacturing SOI devices has recently undergone significant changes. These changes have occurred since the development of three dimensional integrated circuits. However, certain problems have arisen in obtaining a yield good enough for workable SOI devices particularly where the poly-silicon or amorphous silicon (.alpha.-Si) layer is transformed into a single crystal layer by the zone melting recrystallization process.
In carrying out zone melting recrystallization, the prior art has encountered various problems by virtue of stresses occurring from the anomalous 9 % volume expansion during phase changes of the silicon, as well as the large biaxial tensile stresses at the silicon-silicon dioxide interfaces. These biaxial tensile stresses are created by the differential thermal expansion and contraction of the various layers of material in a typical SOI structure (e.g. Si and SiO.sub.2).
Work has been reported by Geis et al, J. Electrochem. Soc., Vol. l29, pages 2812-2818 (Dec. l982) directed to zone melting recrystallization of silicon films using movable strip heater ovens in which an encapsulation of SiO.sub.2 -Si.sub.3 N.sub.4 was attempted. This encapsulation layer was not successful inasmuch as such effects as film agglomeration, film delamination, void formation, and film thickness variation due to mass transport occurred too frequently for practical applications because of the difficulties in controlling sputtering for Si.sub.3 N.sub.4 deposition.
A later effort by Sakurai, reported in J. Electrochem. Soc.: Solid-State Science and Technology Vol. 133, No. 7, pages 1485-1488 (July 1986) also was concerned with the use of capping layers and utilized the same silicon dioxide-silicon nitride layers of Geis. However, in attempting to demonstrate that no measurable impurity redistribution occurred in the substrate underneath the dielectric isolation layer during recrystallization of a 0.4 .mu.m poly-silicon film, Sakurai formed the layer of poly-silicon with a capping layer of phosphosilicate glass (PSG) and an underlying composite layer of silicon nitride/PSG/silicon nitride over an arsenic implanted silicon substrate in order to get higher thermal impedance and to protect the substrate. This experiment was designed to demonstrate 3-D integration feasibility. Sakurai's thin PSG layer by itself, does not hold up to the severe conditions of beam induced zone melting recrystallization of the underlying silicon film so that extensive film delamination and conglomeration can result.
The efforts of the prior art have been unable to prevent large biaxial tensile stresses and to circumvent the deleterious effects of the anomalous 9 % volume expansion of the silicon layer during recrystallization. Accordingly, practical and reproducible SOI devices with consistently high yield have not been formed by the prior art techniques.